Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core

Functional safety is a key requirement in several application domains which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose protecting circuits against single event upset (SEU) faults. In microprocessors, functional may be achieved through multi-core or simultaneous-multi-threading architectures, that broadly classifiable as Double Modular Redundancy (DMR) and Triple (TMR), involving duplication triplication architecture units, respectively. RISC-V plays interesting role this context for its inherent extendability availability open-source microarchitecture designs. work, we present novel way to exploit advantages both DMR TMR Interleaved-Multi-Threading (IMT) microprocessor architecture, leveraging replicated threads redundancy, obtaining system can dynamically switch from case We demonstrated approach specific family cores, modifying proving effectiveness extensive RTL fault-injection simulation campaign.